Microprocessors and input/output (I/O) devices often have different operating capabilities relative to their operating frequency. For example, a microprocessor may be capable of transferring data to or from an I/O device at a much faster rate than the I/O device can receive or transmit data. In order not to slow down the microprocessor, RAMs are frequently used as buffers or interface data storage elements between microprocessors and I/O devices. In this manner data can be transferred between the RAM and the microprocessor at one rate and between the RAM and I/O device at another rate.
A conventional RAM used as an interface is a first-in first-out (FIFO) buffer in which data elements (typically data bytes) are read out in the same order in which they are read into the FIFO. A dual-ported FIFO RAM allows data to be simultaneously read from and written to the buffer. Thus, a fast microprocessor can transfer data into the FIFO at its operating frequency, and a relatively slower I/O device can read the data at its operating frequency. In order to track the location of the next data byte to be written to or read from the FIFO, write and read address pointers are used. The write and read pointers are incremented on each FIFO access, and a byte count for the number of bytes of data in the FIFO is increased or decreased as the amount of data increases or decreases, respectively. The byte count is used by the microprocessor and/or I/O device to indicate when the FIFO should be read and when no more data should be transferred to the FIFO. For example, a fast microprocessor might wait until the FIFO is half full before reading data therefrom.
As with many data transfers, data elements transferred from g FIFO are checked for transmission errors. This may be accomplished by a parity check or other standard error detection technique. When an error is detected, conventional FIFOs retransmit the entire data block which contains the bad data element. Thus, no data elements in a data block may be overwritten in the FIFO until all such data elements have been successfully transferred. This reduces data throughput which may degrade system performance.